The present invention relates to semiconductor devices and, more particularly, relates to improved isolation for semiconductor devices.
Semiconductor devices are employed in various systems for a wide range of applications. An important type of semiconductor device is the transistor. Transistors are ubiquitous in electronics and are often used as part of larger devices or systems. For example, transistors may form part of a logic device or may be used to create memory cells such as dynamic random access memory (“DRAM”).
A simple DRAM cell may include one transistor and one capacitor formed on or within a semiconductor substrate. A DRAM cell formed on the semiconductor substrate is known as a stacked memory cell, and a DRAM cell formed within the semiconductor substrate is known as a trench memory cell. The capacitor stores a charge to represent a data value. The transistor allows the data value to be refreshed, read from, or written to the capacitor.
FIG. 1 illustrates a conventional DRAM memory cell 100 including a capacitor 110 and a transistor 120. The capacitor 110 includes a first electrode 112 and a second electrode 114, which are typically separated by a dielectric (not shown). The transistor 120 includes a source (or drain) 122 connected to the second electrode 114. The transistor 120 also includes a drain (or source) region 124 connected to a bit line 132, as well as a gate region 126 connected to a word line 130. The data may be refreshed, read from or written to the capacitor 110 by applying appropriate voltage to the bit line 132 and/or the word line 130.
A series of DRAM cells or logic devices are typically formed together in a memory chip or in a chip with an embedded memory. One method of forming more memory cells or logic devices is to reduce the size of each device. As device size decreases, for example, the memory capacity of a DRAM chip increases. However, decreasing the size of the device or portions of the device can have adverse consequences. For instance, in a trench memory cell, misalignment may occur between the word line and the edge of the trench. The misalignment commonly leads to increased cell leakage caused by leakage between the source and drain regions. The leakage between the source and drain of the transistor is present in both stacked and trench DRAMs.
A key challenge to the continued scaling or increased density of memory calls is to maintain low leakage between source and drain of the pass transistor 120 so that charge from the capacitor 110 does not leak before it is refreshed. Vertical transistors have thus been proposed in both stacked and trench DRAM cells which utilize the third (vertical) dimension to decouple the pass transistor gate length from the dimensions on the surface of the ship. This decoupling allows for increased density of the memory cells by burying the source/drain 12 below the silicon surface. In the case of stacked cell, the bit line is buried i.e., the junction 124 is buried whereas for a trench cell the capacitor is buried i.e., the junction 122 is buried.
In present DRAMS, high density is achieved by making the bit line contact to 124 borderless to the word line 130 of a trench DRAM cell. For stacked DRAMs, the contacts are borderless to the word line 130. For DRAMS with vertical transistors, the bit line contact or the stacked capacitor contact must also be borderless to the vertical gate polysilicon. Consequently, inner spacers have been proposed. It is therefore desirable to provide a process for making such inner spacers.
The presence of leakage between source and drain is also a problem for conventional logic chips. In addition, logic chips also suffer from increased leakage through the gate insulator. Raised source-drain structures have been proposed to deal with the first problem but usually call for epitaxially growing Si in the source-drain region which is prone to defects. Accordingly, high-K gate dielectrics have been proposed to address the problem of increased gate leakage, but such dielectrics are better utilized with a non-conventional damascene formed gate structure. It is thus desirable to provide a structure and a method of forming defect-free raised source-drains with high-K gate dielectrics and damascene formed gates on logic chips.
U.S. Pat. No. 5,998,835 to Furukawa et al. describes a known raised-source drain structure but does not teach encapsulated spacers or damascene gates on the high-K gate dielectrics. The disclosure is incorporated herein by reference. Thus, a need nevertheless exists for semiconductor devices having improved isolation.